Call for Papers
The eleventh workshop on RTL and high level testing (WRTLT'10) will be hold in conjunction with the 19th Asian Test Symposium (ATS'10) in Shanghai, China. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.
Topics of interest include (but not limited to):
- Functional fault modeling
- RTL ATPG
- RTL DFT
- RTL BIST
- Relationship between RTL and gate level testing
- Design verification
- High level test bench generation
- SoC testing
- High level approach for testing
- Microprocessor testing
Authors are invited to submit paper proposals for presentation at the workshop. The proposal
may be an extended summary (1,000 words) or a full paper and should includes: title, full name
and affiliation of all authors, 100 words abstract and 5 keywords. The full mailing address,
phone, fax and email address of the corresponding author should be specified. All submissions
must be made electronically in PDF format. Please visit our web site (http://wrtlt10.shnu.edu.cn)
for full submission instructions and updated information on the workshop.
Papers will be reviewed internationally and selected based on their originality, significance,
relevance, and clarity of presentation. All accepted papers will be offered the possibility to be published in Journal of Shanghai Normal University.
The submissions will be considered evidence that upon acceptance the author(s) will prepare the
final manuscript on time for inclusion in the digests and will present the paper at the workshop.
Submission deadline: July 27, 2010
Notification of acceptance: August 31, 2010
Camera-ready copy: September 20, 2010