The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing.
The eleventh workshop on RTL and high level testing (WRTLT'10) will be hold in conjunction with the 19th Asian Test Symposium (ATS'10) in Shanghai, China. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.
Submission deadline: July 27, 2010
Notification of acceptance: August 31, 2010
Camera-ready copy: September 20, 2010
Areas of interest includes but not limited to:
- Functional fault modeling - RTL ATPG
- RTL DFT - RTL BIST
- Relationship between RTL and gate level testing - Design verification
- High level test bench generation - SoC testing
- High level approach for testing - Microprocessor testing